The present invention relates to semiconductor power device technology and more particularly to improved trench-gated power devices and manufacturing processes for forming the same.
Power MOSFETs (metal oxide semiconductor field effect transistors) are well known in the semiconductor industry. One variety of power MOSFETs is the vertically-conducting “trench MOSFET” (e.g., trench DMOS, trench FET, UMOS, etc.). Generally, the trench MOSFET includes vertical trenches formed in a semiconducting layer. The semiconducting layer is disposed on a substrate (i.e., wafer) that forms the trench MOSFET drain. Each trench includes a polysilicon gate insulated from the sidewalls of the trench by a dielectric, generally an oxide. Source regions of the MOSFET flank each side of trenches. Trench MOSFETs rely on current flow though a channel formed between the source regions and the drain region. The current flow is controlled by a potential placed on the polysilicon gates.
Conventionally, the polysilicon gate must be connected to the leads of the device package. To accomplish this, the gate extends out of the trench and up onto an insulating layer formed on the surface of the substrate. An overlying metal layer is then formed on the surface of the substrate to electrically connect the source mesa regions and the polysilicon gates on the surface to bonding pads or to bonding structures of the device. A dielectric layer is used to insulate the polysilicon gates in the trenches from the overlying metal layer. The overlying metal layer is masked and etched to separate the metal layer connecting the gates from the metal layer connecting the source regions. In a conventional configuration, the metal layer forms a bus for connecting the source regions and another bus connecting the gates.
Current fabrication processes used to fabricate trench-gated MOSFETs have proven challenging for the semiconductor industry. Generally, the more complex the device, the more complex the process steps. The more complex the process steps the more likely a process error will occur. For example, conventional processes for power MOSFETs often involve the creation and deployment of several masks to accommodate forming complex structures such as active gate trenches. Using multiple masks to etch adjacent trenches of varying dimensions has proven to be difficult due to errors introduced by the mask dimensions and/or alignment thereof at each masking step. A single mask misalignment can potentially ruin an entire array of MOSFETs.
Variations in the topography of the substrate surface make it difficult to uniformly deposit onto or etch material from the wafer surface. For example, variations in topography make it difficult to bring the entire surface of the substrate in the depth of field of photolithography system, or selectively remove material based on position. Variations in semiconductor device fabrication often leads to variations in device electrical performance such as drain-to-source resistance (Rdson), drain to gate charge (Qgd), and the like. Therefore, providing a uniform substrate surface at various fabrication stages is essential in providing accurate electrical characteristics of power MOSFETs.
There is therefore a need for cost effective fabrication processes and substrate structures that minimize or eliminate device defects during the fabrication of vertically aligned trench gated MOSFETs while enhancing the electrical performance characteristics thereof.